AI-era chips will be defined by custom compute, memory proximity, efficiency: Executives

BENGALURU: The next generation of AI chips will increasingly be designed around specific workloads rather than raw compute alone, as power consumption, memory movement, latency and system integration become equally important constraints, semiconductor leaders said at the ETElectronicsWorld Design & Verification Summit 2026.

During the expert panel, “Designing Chips for the AI Era: The Next Wave of Compute Innovation,” moderated by M Chockalingam, technology director, Nasscom AI, executives from MIPS, Infineon Technologies, Silicon Labs, MiPhi Semiconductors, TechCrafter.cps and Renesas discussed how AI is changing both semiconductor architectures and the process of designing them.